The idea is to create a class of accelerators for IITB's Ajit processor. Ajit is a 32-bit processor which implements the SPARC-V8 instruction set. The first accelerator in that effort is a crypto-accelerator which which will implement AES and RSA algorithms and a PUF.
The hardware consists of two modules -- system and core. The system module handles integration with Ajit. It will implement the AFB (Ajit FIFO Bus), and a DMA engine to interface with memory. In addition there will be a bank of programmable registers for controlling the core and interrupt source(s). This module is expected to be reusable across accelerators.
The core module implements the core pipelines for the particular acclerator -- in this case, the AES and RSA pipelines. The plan is to create a first working system which integrates a NIOS processor on a DE-NANO board to the accelerator with a single crypto pipeline.