RISC-V is an open ISA based on the RISC approach, which was originally created at UC, Berkeley. Since then its maintenance and development is handled by the RISC-V Foundation. There are several open-source implementation of the ISA available online. The instructions which follow are for using the implementations from Bluespec, Inc. as I am quite familiar with them.
There are two aspects to designing an embedded system using the RISC-V cores -- the core itself along with a simulation environment, and the RISC-V toolchain. The latter is maintained by the RISC-V Foundation and is independent of the particular implementation (usually).
The RISC-V toolchain comprises of compilers, assemblers and linkers (the gcc toolchain) for the RISC-V ISA. You need these to compile a C/ASM program to object code/ELF which can be understood by a RISC-V core/implementation. The toolchain has been installed on 10.107.88.32:/opt/cross-compilers/rv64gc. In order to use these tools, you need to add /opt/cross-compilers/rv64gc/bin to your PATH. There is a sample setup script in 10.107.88.32:/home/nirajns/setups/riscv.setup for your reference
A word about the rv64gc moniker. This toolchain supports the base 64-bit RISC-V ISA plus extensions: A, D, F, M and C. Please refer to the ISA's reference guide for details about these extensions.
In addition to the toolchain, you may require the following tools depending on your development flow:
The Flute is a 5-stage RISC-V implementation which can be configured to support different extensions of the RISC-V ISA. At its fullest, it support RV64GC. It supports an optional MMU, and can boot Linux. The core and the associated simulation environment is available for download here.
Once you clone the repository, just follow the instructions on the README to run a program on the core. It comes with a minimal SoC comprising of a memory controller and a UART.