Tejeshwar Bhagatsing Thorawade

Contact Email: tejeshwar[at]iitb.ac.in Computer Architecture and Dependable Systems Lab, Department of Electrical Engineering, Indian Institute of Technology Bombay.

Research Interests

• Micro-architectural Security

• DRAM Security

• Memory Subsystem Design

Publications

• V. Venkitaraman, T. B. Thorawade, M. Tandon, K. Kokkiligadda, V. Singh, and J. Patel. "LiC: Low-Cost Cache Replacement Algorithm for All Cache Levels" , in 2025 IFIP/IEEE 33rd International Conference on Very Large Scale Integration (VLSI-SoC), Puerto Varas, Chile, 2025.

• T. B. Thorawade, K. Kokkiligadda, V. Venkitaraman, Ankith, Newton, and V. Singh. "Spin-TLB: STT-RAM-based Translation Hierarchy for Server Applications in CPUs" , in 2025 29th International Symposium on VLSI Design and Test (VDAT), Chandigarh, India, 2025.

• V. Venkitaraman, R. Ravi, T. Thorawade, N. Boran, and V. Singh. "SCAM: Secure Shared Cache Partitioning Scheme to Enhance Throughput of CMPs" , in Proceedings of the 22nd International Conference on Security and Cryptography (SECRYPT), Bilbao, Spain, 2025, pp. 144–155.

• V. Venkitaraman, S. Bhargava, T. B. Thorawade, K. Kokkiligadda, R. Kumar, and V. Singh. "RRR: Robust Runtime Reconfigurable Shared Cache Management Scheme for GPGPUs" , in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1–5.

• T. B. Thorawade, P. Yeola, V. Venkitaraman, and V. Singh. "S-Clflush: Securing Against Flush-based Cache Timing Side-Channel Attacks" , in 2024 IEEE 36th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Hilo, HI, USA, 2024, pp. 218–228.

PMRF Teaching

• Computer Architecture (Autumn 2025-26)
  Department of Computer Science & Engineering, National Institute of Technology Calicut, Calicut, Kerala. (31 hours)
  

• Computer Architecture and Design (Spring 2024-25)
  Department of Computer Science & Engineering, National Institute of Technology Calicut, Calicut, Kerala. (31 hours)
  

• Computer Architecture (Autumn 2024-25)
  Department of Computer Science & Engineering, National Institute of Technology Calicut, Calicut, Kerala. (30 hours)
  

• Hardware Lab (Spring 2023-24)
  Department of Computer Science & Engineering, National Institute of Technology Calicut, Calicut, Kerala. (30 hours)
  

• Logic Design Lab (Autumn 2023-24)
  Department of Computer Science & Engineering, National Institute of Technology Calicut, Calicut, Kerala. (34 hours)
  

• Hardware Description Languages (Spring 2022-23)
  Department of Technology, Shivaji University, Kolhapur, Maharashtra. (16 hours)
  

• Processor Design (Autumn 2022-23)
  Department of Technology, Shivaji University, Kolhapur, Maharashtra. (32 hours)
  

• VHDL Programming (Spring 2021-22)
  Department of Technology, Shivaji University, Kolhapur, Maharashtra. (20 hours)
  

Educational Background

• Ph. D. in Electrical Engineering from Indian Institute of Technology, Bombay (2021-present)
  

• B. Tech. in Electrical Engineering with Honours and with Minor in Systems and Control Engineering from Indian Institute of Technology, Bombay (2014-2018)
  

Teaching Assistantship

• EE 748: Advanced Topics in Computer Architecture (Autumn 2025-26)
  

• EE 739: Processor Design (Spring 2024-25)
  

• EE 748: Advanced Topics in Computer Architecture (Autumn 2024-25)
  

• EE 739: Processor Design (Spring 2023-24)
  

• EE 748: Advanced Topics in Computer Architecture (Autumn 2023-24)
  

• EE 739: Processor Design (Spring 2022-23)
  

• EE 224: Digital Systems (Autumn 2022-23)
  

• EE 309: Microprocessors (Spring 2021-22)
  

• EE 230: Analog Lab (Autumn 2021-22)
  

Course Work

• CS 745 (Audit): Principles of Data and System Security
  

• CS 614: Advanced Compilers
  

• EE 671: VLSI Design
  

• EE 899: Communication Skills
  

• CS 773: Computer Architecture for Performance and Security
  

• EE 691: R & D Project
  

• EE 705: VLSI Design Lab
  

• EE 709: Testing and Verification of VLSI Circuits
  

• EES801: Seminar
  

• CS 683: Advanced Computer Architecture
  

• EE 721: Hardware Description Languages
  

• EE 748: Advanced Topics in Computer Architecture
  

• EE 789: Algorithmic Design of Digital Systems
  

Professional Experience

• Chip Design Verification Engineer (July, 2018 - July, 2021)
  Samsung Semiconductor India R&D. (Bangalore, India)
  

• Intern (May, 2017 - July, 2017)
  YOLO Health. (Pune, India)