At IIT Bombay
Sensor readout systems: CMOS production line, sensor non-idealities, trimming.
Sensor system specifications. Characterizing a readout system: SNR, Noise, SNDR, DR, coherent sampling.
CMOS layout considerations: mismatch, modelling, PVT, layout techniques, random vs systematic offset.
Auto-zeroing (AZ) techniques and trade-offs, Ping-pong AZ, Correlated double sampling (CDS).
Chopping Techniques and non-idealities, chopper layout consideration and design.
Resistive chopper based instrumentation amplifier (IA), current-domain chopper based IA,
Ping-pong AZ based IA. Capacitively coupled chopper amplifier (CCC)-OTA: differential and common-mode
frequency response, noise analysis, CMRR, ICMR, flicker noise and offset reduction, settling-time.
Capacitvely-coupled chopper IA (CCC-IA),input impedance boosting.
DC-Servo loops, dynamic element matching.
Assignments: Modelling and characterization of sensor readouts in Matlab
Course Project: Design of a Capacitive coupled chopper amplifier for temeperature sensor in Cadence with GPDK.
Basics on variability in CMOS integrated circuits: CMOS process corners, mismatch and its modelling.
Nyquist-rate data converters: quantization, SAR, flash and single/dual slope converters, application space and
drawbacks. Modelling on Python/Matlab, Fourier – continuous and discrete (time and frequency),
avoiding spectral artifacts, ADC characterization.
System modelling of Delta Sigma modulators: Nyquist rate sampling, oversampling and its effects, quantization +
oversampling, concept of noise shaping, noise shaping filter implementation, evaluation of signal transfer function
(STF), noise transfer function (NTF).
First-order delta sigma modulators (DSM): with single-bit and multi-bit quantizers, performance evaluation of
first order DSM, higher-order DSMs pros and cons: stability, non-linearity, maximum stable amplitude,
effect of process variations, design of custom NTFs, continuous-time vs discrete time DSM, dynamic range
scaling, cascade of integrator feed-forward vs feedback comparison. Dynamic element matching (DEM).
Delta Sigma ADC design: Schreier software toolbox design methodology, mapping to hardware, CMOS integrator,
summer, digital-to-analog converter (DAC) implementations, design of CIFF and CIFB architecture examples.
Delta Sigma (DS) DAC: introduction, application space, correlation of delta sigma ADC design flow with
delta sigma DAC design flow, example of a DS DAC design flow.
Incremental Delta Sigma (IDS) converters: need for IDS converters, sensor applications associated with
IDS, IDS vs DS modulators, design flow correlation between IDS and DS modulators.
Applications and Case studies
Assignments: Modelling and characterization of Nyquist and oversampled ADCs, mismatches. Design of a CTDSM in Cadence with ideal blocks.
Course Project: Design of a higher order CTDSM with practical DAC, quantizer and loop filter in Cadence with GPDK.
Theory:
Embedded systems overview: architecture basics, analog/mixed-signal chain, ADC and DAC
considerations for embedded system design, embedded processor overview – CPU vs DSP vs ARM, RISC vs CISC,
ARM Cortex M and A series micro-architecture and components.
SoC memory subsystems: Flash, DRAM, SRAM, Cache,Stacks, Memory maps.
ADC and DAC interfacing: Quantization, SNR consideration, full-scale vs ENOB, trade-offs with
sampling frequency, memory, ENOB and power.
I/Os: Multi-standard I/Os, GPIOs, high-speed transceivers; CMOS, LVDS, LVPECL signalling, parallel interfacing.
Serial interfacing: SPI, RS232, RS485, I2C, UART, CAN, USB.
ARM architecture (v8): instruction sets (standard ARM, THUMB and Jazelle),
Embedded software and operating system,
Introduction to Zynq 7000 series SoC: Processing system (PS) side – Cortex A9 and Programmable logic (PL)
– FPGA, DSP, RAM; general purpose AXI ports, high-performance AXI ports.
SoC interconnect (PS-PL interconnect): AXI signalling, AXI4, AXI4Lite, AXI4Stream, SPI-AXI4 stream
implementation for real time data acquisition, direct memory access (DMA), comparison of data movement
methods (CPU programmed I/O vs PS DMA vs PL AXI_HP_DMA vs PL AXI_GP_DMA), memory map.
Lab:
TIVA-C based embedded experiments:
Introduction to TIVA-C and CCS, Parallel I/O and basic arithmetic operations, using on-chip ADC, DAC interfacing
, Assembly level programming.
Zynq-7000 base embedded experiments:
baremetal applications, hardware accelerators for ML use-case. Data movements between PS-PL.
Course Project: Design of embedded system using TIVA-C or Pynq-Z2 (accelerators for image, audio, biomedical signal processing, classification and display).
Will upload images from few projects in some time.
CMOS: Behaviour & Spice Modeling, Layout/Stick Diagram, Interconnects: Wireline models, CMOS Inverter,
Static CMOS Logic gate design, Dynamic CMOS logic design, CMOS sequential logic design, Custom/Semi-custom ASIC
Design, Design of standard cells, Standard Cell Library, Standard cell views and their creation
(.v/.vhd, .lef, .lib, .gdsII, .spi/.cdl), IO Library, IP libraries: Adder architectures, Multiplier architectures,
Memory: 6T cell based SRAM Design (single port and dual port), 8T cell based register file design, DRAM,
Timing Issues in Digital Circuits (slack, slew, skew), Design Synthesis, Physical Design: Floorplan, power plan, placement,
clock tree synthesis, static Timing Analysis,
RTL to gdsII design use cases and optimization using OpenLane based open source design flow.
Assignments: Design and layout of inverter using Sky130 PDK, design synthesis using Yosys(and abc), RTL to gdsII using Openlane
Course Project-1: Design of standard cell library in Sky130 PDK (spice, layout, characterization (.lib), lef and .v generation).
Course Project-2: Design, synthesis, verification (functional and physical) of complex designs using Openlane flow and Sky130 PDK (will upload
some images later from student projects).
Design and FPGA verification of a RISC-V SoC. Will update more information later.