Devices and System Heterointegration (DESH) Group

IC design and Design-Technology Co-Optimization

Based on the various novel memory and logic devices being developed in the group, we are exploring Design-Technology Co-Optimization framework for In-memory computing systems. This includes:

Development of DTCO flow for Advanced CMOS (2 nm and beyond): GAA and CFET technology.

Chiplet design and testing for Embedded Memory and In-Memory compute chips

RISC-V based SoC with In-Memory compute blocks

Exploration of asynchronous analog neuromorphic chiplet design with novel devices