Devices and System Heterointegration (DESH) Group

Fabrication and Chiplet Integration for AI

The chiplet ICs that we design will be integrated in System-in-Package with advanced 2.5D and 3D integration at the upcoming IITB packaging laboratory by our group.

We are developing fabrication technology for 2.5D/3D integration involving multi-layer routing and through via interposer dies.

Fabrication and Chiplet Integration for Quantum

Quantum computing systems require multiple chips to be integrated tightly along with classical CMOS circuits for a complete standalone computing. These need to work at cryogenic temperatures. Therefore, a 2.5D/3D integration of chips is necessary. In this area we are developing:

Superconducting multi-layer routing process

Superconducting TSV

Superconducting Flip-chip process